This invention relates to timing analyses for determining whether timing requirements are met in electronic designs. More specifically, the invention relates to rapid techniques for performing such timing analyses by recalculating a timing parameter for only a portion of the electronic design.
Electronic design automation (xe2x80x9cEDAxe2x80x9d) is becoming increasingly complicated and time consuming, due in part to the greatly increasing size and complexity of the electronic devices designed by EDA tools. Such devices include general purpose microprocessors as well as custom logic devices including Application Specific Integrated Circuits (xe2x80x9cASICsxe2x80x9d). Examples of ASICs include non-programmable gate arrays, Field Programmable Gate Arrays (xe2x80x9cFPGAsxe2x80x9d), and Complex Programmable Logic Devices (xe2x80x9cPLDsxe2x80x9d or xe2x80x9cCPLDsxe2x80x9d). The design of even the simplest of these devices typically involves generation of a high level design, logic simulation, generation of a network, timing simulation, etc.
Timing analyses or simulations are performed to determine whether a particular design meets timing requirements specified by the designer. Such requirements may be necessary to ensure compliance with the requirements of an application for which the device will be used. Usually, timing simulation cannot be performed until the design has been compiled to the point where various gate level entities (representing at least a subsection of the overall design) are synthesized and placed and the lines therebetween are routed on a target hardware device. This compilation requires that an initial design (or a significant piece of it) be functionally completed.
Quite typically, a designer (or the compiler itself) will modify a design, after an initial compilation. This may be required when a timing simulation or other design analysis conducted after (or as part of) compilation indicates a problem. Or, the product requirements may change in the middle of the device""s development. Regardless of why a design change is necessary, that change requires a recompile. With some or all such recompiles, the designer conducts timing analyses.
In a hierarchical or xe2x80x9ctop downxe2x80x9d design process, initial designs may specify generic logic blocks (e.g., an arithmetic logic unit) without specifying the gate level logic. Other parts of the design may be completed to the gate level. Such initial designs are very coarse; i.e., they are far removed from the final exact hardware layout of the whole device. Results of timing simulations performed after compilation at these early stage designs will necessarily lack precision. The design parameters are not completely defined at the silicon level and the design will likely change/evolve as development progresses. Nevertheless, a timing analysis can be performed on these initial designs in order to determine whether the timing parameters are within the general range (xe2x80x9cballparkxe2x80x9d) specified by the designer. In later stage designs, the timing parameters can be gauged with more precision and accuracy.
If a design is being driven primarily by timing considerations so that the goal is a very fast device, obviously the timing simulations must be performed very frequently during the design process. In this case, a designer may conduct timing simulations with each small design modification. If the design is driven primarily by some other parameter such as logic density, then timing simulations may not be necessary quite as often. But regardless of whether the design is driven more by timing constraints or area constraints, some form of timing analysis must be frequently performed during the design process.
To guide later stages of design and to verify that timing requirements are met, timing analyses are typically performed before, during, and after xe2x80x9cfitting.xe2x80x9d Fitting is a process whereby a compiler fits an electronic design onto a target hardware device. For PLD designs, fitting can be divided into three phases: partitioning, placement, and routing. Partitioning involves grouping logic cells which share common inputs/outputs and/or feed one another. This grouping is intended to minimize the amount of long distance routing. Cells that frequently communicate with each other or share common resources should be placed close together so that most routing is local. During the placement phase, the various logic groups or blocks created during partitioning are assigned to specific geographic locations on a hardware device. Finally, routing makes interconnections between the various logic blocks that are now placed on the hardware device. Normally, the timing of each new xe2x80x9cfitxe2x80x9d of a design is checked.
While the primary goal of timing analyses is to ensure that the resulting electronic design and constituent circuits are meet timing requirements (i.e., they are fast), it is also important to ensure that the timing analyses themselves can be executed rapidly. Each compilation and associated timing simulation consumes significant time, so multiple recompiles/timing simulations translates to significantly longer development times. This can greatly slow the time to market for an integrated circuit under design. Because PLDs rely on a short time to market as a major selling point, slow development can erase any commercial advantage.
The problem is compounded because maximum CPLD device sizes are increasing at a speed slightly greater than that predicted by Moore""s law (i.e., each new chip contains roughly twice as much capacity as its predecessor, and each chip is released within 18-24 months of the previous chip). If compilation time was a linear function of design size then it would be expected that the time to compile the largest device on the most powerful computer would remain approximately constant. Unfortunately, compile times are typically proportional to n2, where n is the number of logic elements on a device. This means that a design twice as big takes four times as long to compile (on a given computer). Consequently, the compile times for the largest devices are accelerating. It is not uncommon for large projects to compile for about 24 hours or more on a modern workstation. Obviously, the fastest compilers (and associated timing simulators) will become critical components of integrated circuit design environments.
It appears that most available design products do not perform timing analysis as rapidly as they might. Therefore, there is a need for more rapid techniques for performing timing analyses in large and/or complex electronic designs.
The present invention provides an xe2x80x9cincrementalxe2x80x9d timing analysis or simulation in which much of the results of a previous timing simulation are used. The previous timing results were obtained for a previous electronic design which was slightly modified by the designer. The portion of the design affected by the modification is identified and its timing is recalculated. The timing for the remainder of the design is left as is from the previous design. This speeds the timing analysis for the modified design because less than the entire design need be considered in the new timing analysis.
In this invention, the timing analyses of interest are performed after considering at least one and usually two xe2x80x9cregionsxe2x80x9d associated with a design change: (1) the region of the design change itself and (2) a possibly larger region having its timing influenced by the design change.
The process of interest is triggered when a xe2x80x9cfirst electronic designxe2x80x9d is converted to a xe2x80x9csecond electronic design.xe2x80x9d This involves taking the first design and modifying a portion of it by refitting that area, changing the logic in that area, or otherwise changing that area. In an important embodiment, it involves refitting the portion. As a result of the modification, some portion of the first design will be modified. That portion is referred to herein as a xe2x80x9cmodified portion.xe2x80x9d The remainder of the design is referred to as the xe2x80x9cunmodified portion.xe2x80x9d Thus, the second electronic design includes a modified portion and an unmodified portion. The modified portion may have had the gates themselves changed, cell fan-in or fan-out changed, the location of a cell changed, etc. In an important embodiment, the modification involves only a change in location of a logic cell. The fan-in and fan-out of the moved cell (as well as the other cells) remain unmodified.
The modification will typically have an affect on timing results. The design system of this invention will store timing results of a xe2x80x9cfirst timing analysisxe2x80x9d performed on the first electronic design. The modification to the first electronic design will typically impact the timing results. The trick here is to determine the timing results of the second electronic design without redoing the entire timing simulation for the second electronic design. To accomplish this, the invention delineates an xe2x80x9caffected portionxe2x80x9d of the second electronic design where the timing results are likely to have been locally changed as a result of the modification. Often the xe2x80x9caffected portionxe2x80x9d will subsume the xe2x80x9cmodified portion.xe2x80x9d Once this affected portion has been identified, the timing simulation of the second electronic design can be streamlined. It involves first calculating a xe2x80x9clocal timing resultxe2x80x9d for the affected portion of the design, and second calculating an xe2x80x9coverall timing resultxe2x80x9d for the second electronic design by using the local timing result and an xe2x80x9cunmodified timing result.xe2x80x9d This unmodified timing result is the portion of the timing result from the first electronic design that corresponds to that location of the first electronic design that lies outside of the xe2x80x9caffected portion.xe2x80x9d
Preferably, the first electronic design is a design of a partially completed ASIC design, such as a PLD design. Often the timing analysis will be performed on a compiled version of the design. Thus, the first timing analysis will be performed on a compiled version of the first electronic design. The analysis results are then stored. Subsequently, the base design is modified to form the second electronic design, which is then recompiled and analyzed per the second timing analysis.
Preferably, the modification to the first electronic design is a refitting of the logic associated with that design. In a particularly preferred embodiment, the refitting involves moving cells such as by repartitioning cells between two logic groups. Each new design (the second electronic design, etc.) may be generated by moving a single cell from one logic block to another, as is performed in conventional partitioning processes. Each cell movement affects the timing by changing the lengths of lines connecting to the moved cell. It also affects the loads on those cells.
In coarse timing analyses (such as those performed relatively early in the overall design process), the timing analysis of the second electronic design may be conducted without regard to the load changes on the lines to and from a moved cell. In one embodiment, such xe2x80x9cload-independentxe2x80x9d analysis requires that the xe2x80x9caffected portionxe2x80x9d of the second electronic design be the fan-out from the output nodes of a cell that has been moved, together with the moved cell itself. For more precise timing analyses (often performed relatively late in the overall design process), the timing analysis of the second electronic design considers the load changes on the lines to and from a moved cell. In one embodiment, such xe2x80x9cload-dependentxe2x80x9d analysis requires that the xe2x80x9caffected portionxe2x80x9d of the second electronic design be the fan-out from the output nodes of all cells that feed the cell that has been moved.
The goal of many timing analyses is to determine whether the overall timing result meets a given timing constraint. Thus, the present invention also provides for comparing the overall timing result (obtained for the second electronic design) with a design constrain. Sometimes the design constraint is not posed in the same timing type or criteria as the type used in the timing analysis. For example, the timing constraint may be specified as Tcycle whereas the timing analysis is conducted with Tpd. When this is the case, it may be convenient to have a preliminary step of converting the timing constraint from a first type to a second type.
This invention also pertains to devices (e.g., PLDs) designed using the timing analyses described herein. Further, the invention covers machine readable media or computer program products having instructions and/or data for implementing the timing analyses described herein.
In another aspect, this invention provides a system for an electronic design automation (EDA) system that includes at least a fitter (which fits logic onto a target hardware device such as a PLD) and a timing analyzer. The timing analyzer in turn includes (i) a xe2x80x9cdelineatorxe2x80x9d which identifies an affected region of a modified design where timing may have been locally changed as a result of a modification from a previous design, and (ii) a xe2x80x9ctimerxe2x80x9d which calculates the timing at nodes within the affected region. The system may also include a database communicating with the fitter and storing design data for the modified design and the previous design.
The timing analyzer may obtain the data it needs in at least two ways. In a first embodiment, it obtains the design data from the database directly, without having the design data past through the fitter. In a second embodiment, it obtains the design data from the database indirectly, via the fitter.
In preferred embodiment, the fitter will be provided as part of an electronic design compiler. The compiler may contain other modules or entities such as a logic synthesizer. In a preferred embodiment, the logic fit by the fitter onto the target hardware device takes the form of logic cells. In this embodiment, the fitter may move one or more logic cells to create the xe2x80x9cmodified design.xe2x80x9d
These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following descriptions of the invention and a study of the several figures of the drawing.